Quick start guide

FPGA design tutorial contents

Digital circuits basics

CMOS logic fundamentals

This chapter of the FPGA design tutorial is devoted to CMOS logic and basic logic gates.

Logic Gates

Almost all modern digital semiconductor devices use CMOS (complementary metal-oxide-semiconductor) logic. The basic CMOS logic element is a MOS field-effect transistor (MOSFET). CMOS logic utilizes two types of transistors: p-type MOSFET and n-type MOSFET.

P-type MOSFET conducts current when the level of gate corresponds to logic "0" ("low"). Conversely, n-type MOSFET conducts when the level of gate corresponds to logic "1" ("high"). Using this information, it is easy to draw a CMOS inverter:

When A is "1", the upper transistor is closed and the lower one is opened, thus inverter output is "0", and vice versa. Thus, a CMOS inverter is a simple logic gate.

Examples of more complex CMOS gates (small circles designate logical inversion):

Notice that p-type transistors are always connected to the positive power source (Vcc) and n-type transistors - to negative power source (Vdd). It is necessary because in order to conduct current MOSFET transistors need charge carriers to be injected from the source, and this type of connection ensures sufficient electrical field for injection.

Latches and Flip-Flops

RS latch

Imagine that we want to make a circuit that is able to hold a specific value written to it. The simplest way to do it would be to use a buffer (amplifier) and to feed its output to the input.

CMOS logic doesn't have a buffer, but it can be made by combining two inverters.

The above circuit will hold any value indefinitely long, but some additional logic is required to write values to the circuit:

This is an RS latch. It has four modes of operation (set by R and S values):

R	S	Q	~Q	state
0	0	not changed	not changed	Keep Q state
0	1	1	0	Set Q to 1
1	0	0	1	Set Q to 0
1	1	N/A	N/A	Forbidden state

In the forbidden states outputs are undefined.

D latch

In real-world designs, RS latch is almost never used because of the possibility of the forbidden state. This drawback is eliminated in the so-called D-latch.

D latch works as follows: when C is "1", Q is set to the value of D, and when C is "0", the Q value is hold constant. It is designated by the following symbol:

D flip-flop

By combining two D latches one can create a D flip-flop which sets output value only during level transitions of C (either from "0" to "1" or vice versa).