CMOS logic fundamentals
FPGA design tutorial contents
Creating a simple FPGA project
The basics of digital circuit design
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This FPGA design tutorial article is intended to provide an introduction to the area of digital circuit design. The information presented here can be applied not only to FPGA design, but to all types of digital circuit design.
Logic gates symbols
As you can see, small circles denote inversion.
Combinational and Sequential Circuits
Combinational circuit is a circuit containing no memory units (such as latches and flip-flops).
Sequential circuit is a therefore a circuit containing memory units. A register (block of flip-flops or latches) is an essential part of a typical sequential circuit. In a sequential circuit registers are controlled by a clock signal. The set of registers controlled by one clock signal is called a clock domain. Complex circuits can have multiple clock domains.
Complex logic designs can be split into combinational logic sub-circuits communicating via registers.
Timing requirements in synchronous circuits
The following rules apply to synchronous circuits:
- Setup time (ts). All register inputs must be constant during this time before a corresponding clock edge.
- Hold time (th). All register inputs must be constant during this time after a corresponding clock edge.
There are two other effects that must be taken into account when elaborating sequential circuits:
- Clock skew is an effect of non-simultaneous clock switching at the inputs of different registers (controlled by one clock signal).
- Clock jitter is an effect of phase noise in a clock signal.
Thus a maximum propagation delay of a combinational circuit must satisfy the following condition:
tpmax ≤ tclk - ts - Δt,
where tclk is a clock period, ts is a setup time and Δt accounts for skew and jitter.
Typical Logic Primitives
There are many standard logic primitives used by almost all digital designs.
A multiplexer is a device which selects from a number of input channels (selection is made based on special control signal).
For example, the output of the multiplexer on the picture above is determined by a C signal: if C="00" then Z=D0, if C="01" then Z=D1 and so on.
Gate-level schematic of this multiplexer is shown below:
A shift register can be implemented as a chain of flip-flops:
On a clock edge each flip-flop is assigned a value of the previous one (and zeros flip-flop is assigned a value of DIN). In order for this circuit to work, obviously, flip-flop switching delay plus propagation delay must be greater than flip-flop's hold time.
Let's have a look on a 1-bit adder, which generates 1-bit sum and a carry bit.
Several 1-bit adders in a chain make a n-bit adder (4-bit adder shown as an example):
COUT signal can be used to cascade multiple adders.
Example: an accumulator
Logic primitives can be used to create more complex circuits. For instance, let's consider an 4-bit accumulator (a synchronous device which adds input value to its internal value). Obviously, it can be made of a 4-bit adder and a 4-bit register.
Our accumulator should have the following ports:
- DIN - Data Input;
- DOUT - Data Output;
- CLK - Clock;
- CLR - Asynchronous clear (set register to 0);
Instead of drawing a schematic, one can write HDL (VHDL or Verilog) code to describe the device. VHDL code for our accumulator is below.
library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_unsigned.all; entity accumulator is port ( DIN: in std_logic_vector(3 downto 0); DOUT: out std_logic_vector(3 downto 0); CLK: in std_logic; CLR: in std_logic ); end entity; architecture behavioral of accumulator is signal val: std_logic_vector(3 downto 0); begin process (CLK,CLR) is begin if CLR='1' then val<="0000"; elsif rising_edge(CLK) then val<=val+DIN; end if; end process; DOUT<=val; end behavioral;
One can see that VHDL is somewhat similar to conventional programming languages. Hardware description languages will be considered in more details in the further articles.