FPGA design tutorial contents

CMOS logic fundamentals

FPGA design quick start guide

OK, you decided to start with FPGA design. In this article you will find a general information and references. More details can be found in further chapters of this FPGA design tutorial.

FPGA design involves writing HDL (hardware description language) code, creating testbenches (test environments), synthesis, implementation and debugging.

FPGA design steps

1. Writing an HDL description ("design entry"). HDL is a class of high-level languages which is used to define how the device should work. It can be thought about as a programming language, though significantly different from the conventional programming languages. The most frequently used hardware description languages are VHDL and Verilog.
2. Writing a test environment. It is almost impossible to create a fully correct HDL design at once. Therefore, it should be tested for possible errors. Whereas in the area of software development a program can be tested by simply running it, testing FPGA design involves writing a dedicated test environment. Test environment can be written in HDL (VHDL/Verilog), or in SystemC (SystemC is a special class library for C++ with the support for hardware signal simulation). A test environment usually includes a behavioral model, which is a higher-level, non-synthesizable device description used to verify HDL design correctness.
3. Behavioral simulation is used to verify the HDL description against the corresponding behavioral model (using test environment). Most design errors are fixed at this stage.
4. Synthesis is an automated process of converting a high-level HDL description to a machine-readable circuit description (a so-called netlist). Although synthesis of a correctly written HDL code shouldn't be a problem, some errors uncaught by behavioral simulation can appear at this stage.
5. Implementation is a process of converting netlist to an FPGA configuration bitstream (tailored for specific FPGA device).
6. Post-implementation simulation is used to verify the implemented design (taking switching and propagation delays into account) against the behavioral model. This step can be omitted for simple designs.
7. Testing a produced bitstream in hardware.

Software

FPGA design is impossible without specialized vendor-specific EDA (electronic design automation) tools:

• Xilinx ISE (Integrated Software Environment) for Xilinx FPGAs,
• Quartus II for Altera devices,
• Libero for Actel devices.

These tools are not cheap, but Xilinx and Altera provide limited free downloadable versions of their products:

• Xilinx ISE WebPack
• Quartus II Web Edition

Free versions have all the necessary basic functions, but can be used not for all FPGA devices (only for low-to-medium density FPGAs) and don't include some advanced features.

HDL Languages

Both VHDL and Verilog are RTL (register transfer level) languages. Register transfer level is a level of digital circuit design based on registers an combinational logic functions. There are other design levels, both higher-level (architecture level) and lower-level (physical layout level).

There are pretty much resources about VHDL and Verilog on the Web. Some useful links are provided below.

• VHDL Tutorial
• Another VHDL Tutorial
• The Designer’s Guide to Verilog

Hardware

The simplest way to test your FPGA design in hardware is to use a prototyping board (or evaluation board). Prototyping/evaluation boards include FPGA chip and all the supplemental circuitry needed for it (power sources, clock generators etc).

Xilinx and Altera sell a range of evaluation boards:

• Xilinx development boards
• Altera development kits