FPGA design flow

Workflow

We use a process-based workflow for FPGA design service. All the processes are thoroughly documented in order to optimize costs and ensure superior quality. Our team can get involved in the design process at any stage.

1. The FPGA design process begins from writing a functional description containing detailed requirements for FPGA-based circuit. We can start design on basis of a functional description prepared by the customer. Alternatively, we can create the functional description document based on the customer's demands expressed in any form. At no time will we share your information with anyone without your explicit permission.
2. Our team will need a few days to analyze requirements and to evaluate the necessary amount of resources. Then we'll need to agree upon conditions, including time constraints and price.
3. In order to reduce time-to-market, we run the following processes in parallel:
   • Writing a synthesizable RTL (register transfer level) description (either on Verilog or VHDL) of the device, which is needed to produce FPGA bitstreams.
   • Writing a behavioral model, which is used to verify that the design meets its requirements.
   • Writing a verification plan and a corresponding verification environment which describes and implements the method of proving the design correctness.

1-CORE Technologies provides high quality and cost-effective FPGA design services.

4. After RTL description has been written and verified, it is synthesized and implemented with the corresponding toolchain (usually we use Synplify for synthesis and vendor-specific tools for implementation, but this can be changed of the customer has specific demands). The implemented netlist is once again checked against requirements.
5. The RTL verification is performed by the dedicated Validation and Verification Department. This approach significantly reduces the probability of the design error since no RTL (VHDL, Verilog) designer tests his own code.

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